1. Field of the Invention
The present invention relates generally to any DLL (Digital Locked Loop) architecture requiring the generation of multiple timings (timing signals), and more particularly pertains to a simple modular DLL architecture for an eDRAM (embedded Dynamic Random Access Memory) capable of producing any required number of eDRAM timings.
The present invention is applicable generally to any DLL (Digital Locked Loop) architecture requiring the generation of multiple timings, and is applicable to memory products in general, for example to provide timings for memory array cores and for input and output data, including embedded and non-embedded DRAMs and SRAMs (Static Random Access Memories) and memory controllers.
2. Discussion of the Prior Art
DLL (Digital Locked Loop) architectures are frequently used to produce required timing signals; however, the use of several DLLs to accommodate multiple timing signals is expensive in terms of real estate on the chip.
The embedded DRAM design for one present state of the art ASIC (Application Specific Integrated Circuit) demands a simple architecture capable of producing any required number of embedded DRAM timings.
FIG. 1 illustrates a typical prior art DLL implementation for use in a memory product, and FIG. 2 illustrates timing waveforms illustrative of the operation of the prior art DLL implementation of FIG. 1.
Referring to FIG. 1, a variable delay line 1 is used to delay an edge of an incoming clock signal In by a desired amount. The variable delay line typically comprises either a variable number of fixed delay elements or a fixed number of variable delay elements. Typically a Mimic circuit 2 is used to determine how far ahead of the next clock edge an internal clock needs to transition. This is illustrated in FIG. 2 by the designation Mimic Delay which shows the clock edge of the Result clock transitioning a given time ahead of the clock edge of the Out clock. It is common in synchronous chip designs to require a synchronous circuit output be aligned or lined up with an external clock edge. A mimic circuit provides a fixed time delay which is a mimic of a parasitic circuit delay, and is used to determine when to drive the mimic circuit input so that the mimic circuit output and the synchronous circuit output are properly aligned with the external clock.
The output signal Out from the mimic circuit 2 should be delayed 360° with respect to the main clock signal In, as illustrated in FIG. 2 by the designation Total Delay=1 cycle. The main clock input signal In and the output signal Out from the mimic circuit 2 are compared by a Phase Compare circuit 3, and the Phase compare circuit determines if the delay is too little or too much relative to the desired 360° delay phase shift. The output of the phase compare circuit is directed to a Delay Control circuit 4 which increases or decreases the delay through the Variable Delay Line 1. When the phase of the system is locked, the output signal Result will be the desired Mimic circuit delay before the next clock cycle of In. This can then be used to time output data from a circuit, for example. It should be noted that the standard DLL implementation can only use one Mimic circuit, and only offers a single output timing signal Result.